1. Field of the Invention
The invention relates to the fabrication of integrated circuits and to a method for depositing a layer on a substrate and the structures formed by the layer.
2. Description of the Related Art
In the manufacture of integrated circuits, chemical vapor deposition processes are often used for deposition or etching of various material layers. Conventional thermal CVD processes supply reactive compounds to the substrate surface where heat-induced chemical reactions take place to produce a desired layer. Plasma enhanced chemical vapor deposition (PECVD) processes employ a power source (e.g., radio frequency (RF) power or microwave power) coupled to a deposition chamber to increase dissociation of the reactive compounds. Thus, PECVD processes allow deposition to be achieved at lower temperatures than those required for analogous thermal processes. This is advantageous for processes with stringent thermal budget demands, e.g., in very large scale or ultra-large scale integrated circuit (VLSI or ULSI) device fabrication.
The demands for greater integrated circuit densities also impose demands on the process sequences used for integrated circuit manufacture. For example, in process sequences using conventional lithographic techniques, a layer of energy sensitive resist is formed over a stack of material layers on a substrate. An image of a pattern is introduced into the energy sensitive resist layer. Thereafter, the pattern introduced into the energy sensitive resist layer is transferred into one or more layers of the material stack formed on the substrate using the layer of energy sensitive resist as a mask and a chemical etchant. The chemical etchant is designed to have a greater etch selectivity for the material layers of the stack than for the energy sensitive resist. That is, the chemical etchant etches the one or more layers of the material stack at a much faster rate than it etches the energy sensitive resist to prevent the energy sensitive resist material from being consumed prior to completion of the pattern transfer.
A hardmask can be over the exposed material stack to enhance patterning and etching of feature definitions in the material stack. The hardmask is resistive to damage and deformation. The hardmask protects the underlying material stack during subsequent material deposition and planarization or material removal processes, such as chemical mechanical polishing techniques or etching techniques, to reduce defect formation and feature deformation. The hardmask may then be removed following planarization prior to subsequent processing of the substrate.
One material of interest as a hardmask is amorphous carbon. Amorphous carbon has a low dielectric constant (i.e., k<4) and a sufficiently high resistance to removal from etching and polishing techniques for performing as a hardmask. The use of amorphous carbon in semiconductor processing is favorable because it provides good etch selectivity with oxides and metals and is also an anti-reflective coating (ARC) material at deep ultra-violet (DUV) wavelengths. In addition, it is easily stripped away after pattern transfer. Further, it enables gate lengths at less than 100 nm (e.g., less than 60 nm) and contact holes at less than 150 nm (e.g., less than 110 nm) with aspect ratios of more than 5:1 (e.g., more than 8:1).
When depositing an amorphous carbon film on a substrate at a lower deposition temperature, it was surprising to find carbon particles on the substrate surface, which are actually the reactive precursor compounds falling down or sticking onto the deposited carbon material. In contrast, the sources of particle contamination on a substrate for a typical deposition of a material layer typically come from degraded chamber wall, degraded chamber part components, degraded ceramics or metal parts, o-rings, and/or other film material before deposition.
As shown in FIG. 1, during the deposition of an amorphous carbon film on a substrate, it was unexpected to observe carbon particle contamination having a size of about 0.12 μm or larger or about 0.16 μm or larger at a deposition temperature of about 500° C. or lower, such as at around 400° C. or around 450° C. In contrast, at a deposition temperature around 550° C., no carbon particles are seen on the wafer. Therefore, as the processing temperature is decreased from about 550° C. to about 400° C., the number of particles resulting from the deposition increases. This is a problem when low temperature deposition is required to be suitable for various applications, such as aluminum applications.
The applications of using amorphous carbon as a hardmask are widened by adjusting the deposition parameters and thus the film property of the deposited amorphous carbon film. For example, it can be used in front end processing, such as polysilicon gate or oxide contact etch patterning. It can also be used for back end DRAM processing where the underlying material is aluminum, using a lower deposition temperature. However, particle contamination increases as processing parameters change. In addition, decreasing the deposition temperature decreases the absorbance of the film as shown in FIG. 2. FIG. 2 demonstrates the correlation between the deposition temperature and light absorption coefficient, k, of the deposited amorphous carbon film at two different light wavelengths of 248 nm (square dots) and 633 nm (diamond dots). In situations requiring a more transparent film, desired lower extinction coefficient (k) values for the absorbance of the film can be achieved by depositing at lower temperatures. This can be beneficial when performing wafer alignment in preparation for lithograthy because alignment marks may not be detectable if the carbon film is too absorbing. Also, in order to increase the deposition rate of amorphous carbon and thus the throughput of substrate processing, it is preferred to include a lower deposition temperature, as shown in FIG. 3. Thus, it is desired to develop a deposition process for amorphous carbon to reduce the particles generated on the surface of the substrate at a low deposition temperature.